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151	Optimizer Plans, Directives, and SQL Tracing OPTCOMPIND DIRECTIVES EXT_DIRECTIVES11 OPT_GOAL IFX_FOLDVIEW10 Add to Reading List Source URL: www.iiug.org Language: English - Date: 2011-06-16 23:04:38 Relational database management systems CPU cache Cache Central processing unit Computer memory IBM Informix Paging
152	Operational Intensity  Design of Parallel and High-Performance Computing Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-11-23 12:29:14 Sandy Bridge Intel Core Nehalem Cache Central processing unit Computer memory Sandy Bridge-E
153	Specialty: "Finance and credit" Semester 1. № Course unit title Add to Reading List Source URL: stu.cn.ua Language: English - Date: 2015-04-11 11:53:16 Actuarial science Financial services Finance Financial system Risk management Insurance Financial intermediary Risk Bank Non-bank financial institution Financial market Central Bank of Armenia
154	Stratified Synthesis: Automatically Learning the x86-64 Instruction Set Stefan Heule Eric Schkufza Add to Reading List Source URL: raw.githubusercontent.com Language: English Instruction set architectures Central processing unit X86 instructions X86 architecture Computer architecture X86 Instruction set Processor register ARM architecture Low-level programming language NOP Intel
155	Reducing Capacity and Conflict Misses using Set Saturation Levels Dyer Rol´an, Basilio B. Fraguela and Ram´on Doallo Grupo de Arquitectura de Computadores Departamento de Electr´onica e Sistemas Universidade da Coru˜ Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2011-06-03 07:07:22 Cache Central processing unit Computer architecture Computer memory CPU cache Virtual memory Cache algorithms Thrashing DSBC Memory hierarchy Microarchitecture Draft:Cache memory
156	Data Sheet PRELIMINARY December 2010 AR9331 Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms Add to Reading List Source URL: www.openhacks.com Language: English - Date: 2013-10-03 09:25:08 Interrupts Instruction set architectures Management Data Input/Output Central processing unit Universal asynchronous receiver/transmitter IEEE 802.11n-2009 IEEE 802.11 Control register MIPS instruction set
157	Energy Efficient Watchpoint Systems MAD WorkshopVasileios Karakostas, Sasa Tomic, Osman Unsal, Mario Nemirovsky, Adrian Cristal Barcelona Supercomputing Center Add to Reading List Source URL: www.mad-workshop.de Language: English - Date: 2016-03-22 12:43:37 Computer memory Cache Computer architecture CPU cache Central processing unit Breakpoint
158	Terms and Conditions Governing Investments in Funds (Previously referred to as ‘DBS Unit Trust Terms and Conditions’) IMPORTANT Clients are requested to read these terms and conditions before completing the Applicati Add to Reading List Source URL: www.dbs.com.sg Language: English - Date: 2015-12-16 04:44:46 DBS Bank Central Provident Fund Investment fund Exchange-traded fund
159	Summary Design of Parallel and High-Performance Computing: Distributed-Memory Models and Algorithms Lecture overview Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-12-07 15:59:39 Parallel computing Matrix multiplication algorithm Bulk synchronous parallel Algorithm NC Central processing unit Communication-avoiding algorithms
160	Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering, Add to Reading List Source URL: www.dcs.warwick.ac.uk Language: English - Date: 2014-11-13 12:51:32 Cache Central processing unit Computer memory Computer architecture Parallel computing CPU cache Locality of reference Benchmark Microarchitecture Instruction set Instruction-level parallelism Draft:Cache memory

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